Daris Chen

Overview

TriCore9 has a 9-bit Instruction Set Architecture (ISA) and is built using System Verilog. It is capable of performing basic operations such as loading and storing data, arithmetic operations like addition and subtraction, and branching for control flow. The CPU design includes components such as an instruction fetch unit, instruction memory, control decoder, register file, arithmetic logic unit (ALU), and data memory. The CPU is simulated using Intel FPGA ModelSim and synthesized with Quartus Prime. The ISA was modeled after the standard MIPS architecture, with modifications to fit the 8-bit data width and 9-bit instruction format. This ISA is capable of handling hamming distance calculations and the multiplication of two and three Two's Complement numbers with a range of [-128, 127]. The assembler for this CPU was custom-built in Python to convert assembly code into machine code that the CPU can execute. (GitHub Link)

Quick Summary

A custom 8-bit CPU with a 9-bit instruction set architecture (ISA) inspired by MIPS.
Capable of executing basic instructions such as load, store, add, subtract, and branch.
Designed and implemented using System Verilog, simulated on Intel FPGA ModelSim, and synthesized with Quartus Prime.
Includes components such as instruction fetch unit, instruction memory, control decoder, register file, ALU, and data memory.
The ISA supports Two's Complement multiplication with two and three terms and can calculate Hamming Distance.
Custom assembler written in Python to convert assembly code into machine code for the CPU.

Key Features

A simple 8-bit CPU designed using System Verilog, capable of executing basic instructions such as load, store, add, subtract, and branch.
There are 4 registers. The architectures supports up to 8 registers, but only 4 are used due to the limited instruction size.
The Data Memory module allows up to 256 instructions, but the ISA's limited instruction size only allows for 64 instructions to be used. This means that programs must adhere to 64 instruction size pages. BEQZ and JUMP instructions are restricted to addresses within the same page. To switch pages, a memory alignment consisting of JUMP instructions or NOPs must be used.
The CPU supports a variety of instructions, including R-type instructions (ADD, SUB, AND, SHL1, SHR1, XOR, ADDC, MOV), J-type instructions (JUMP, HALT), I-type memory instructions (LOAD, STORE, LOADI, BEQZ).
The CPU is capable of performing Two's Complement multiplication with two and three terms, allowing for multiplication of numbers in the range of [-128, 127].
The CPU can calculate Hamming Distance between two 8-bit numbers, which is useful in error detection and correction applications.
A custom assembler is built in Python to convert assembly code into machine code that the CPU can execute, facilitating the programming of the CPU. A general use Instruction ROM is used to read any machine code generated by the assembler.